A processor may have many clocking sources such as phase locked loops (PLLs). For example, in highly integrated System-on-Chips (SoCs), many different types of input-output (I/O) transceivers (or I/Os) are used. These I/Os may require clock signals of different clocking frequencies with low jitter (i.e., high performance clock signals). To achieve low jitter clock signals, inductor-capacitor (LC) PLLs are commonly used. To provide different clocking frequencies, multiple LCPLLs may be used. For example, a first I/O band having multiple I/Os may require a clock with 2.5 GHz frequency and a second I/O band abutting the first I/O band may have multiple I/Os requiring a clock with 2.38 GHz frequency.
However, in tightly packed SoCs where circuits and modules are very close to one another, close proximity of clocking sources is no surprise. When clocking sources such as LCPLLs are close to one another (e.g., in the case of clock sources of abutting I/O bands), the clock sources experience inductive coupling which causes the output frequency of the LCPLLs to drift away from their intended steady state frequency. One way to mitigate the inductive coupling is to separate the LCPLLs by a large distance (e.g., 200 μm or more). However, such a solution is not practical because it increases area of the integrated circuit.